Overview
ASIC Flow, Digital Fundamentals, Verilog constructs for design, Verilog constructs for verification, Memory design and verification, APB protocol learning
For BE/BTech/MTech ECE/EEE students - who want to do Internship, ECE/EEE Engineers seeking career in VLSI industry
Basics of Electronics, Linux commands
The course basically for beginners to expert level in VLSI. The course covers in details about ASIC Flow, Verilog Language, Digital Fundamentals, Combinational circuits, Sequential circuits, APB Protocol.
It has 9 videos each more than 1 hr, with theory explanation and the hands on program execution.
Cadence Xcelium simulator used for Verilog program execution in linux Environment.
The programs are edited in vi editor.
The following are the course topics:
Session 1: ASIC Flow - Architecture, Design, RTL coding, Verification, DFT overview
Session 2: Synthesis, Static Timing Analysis, Physical Design, FPGA Emulation overview, Digital fundamentals
Session 3: Hardware modeling using Verilog
Session 4: Verilog Program Structure
Session 5 : Verilog Language constructs
Session 6: Combinational circuit design and verification using Verilog
Session 7: Sequential circuit design and verification using Verilog
Session 8: Timing and Event scheduling
Session 9: Projects : Memory design, FIFO and codes and simulations
This course is very good for those wants to do internship, want to learn and start career in VLSI. This helps for acquiring domain knowledge in VLSI and seek job in this industry. These basic concepts and language helps to attend interviews.
The course is designed and delivered by an ASIC Design and Verification Expert worked more than 2 decades in the Semiconductor Industry
VLSI Mentor
- 20+ Years in ASIC Design and Verification and handling end to end chip design.
- Founder of VLSI Design Services company - Excel VLSI
- Extensive ASIC Design and Verification Execution Skills with hands on experience in:
o IP/Block design Verification using - Verilog, System Verilog and UVM
o VIP Development
o Code coverage and functional coverage Metrics.
o Development of test plans and randomized/methodology based test environments
o SoC Verification using C/C++
o Gate Level Simulations at chip level
o Automation scripts for tool flows.